Resources

In the past, you probably only focused on MSU usage during your peak 4HRA. Now, thanks to IBM's Software Consumption, paying more attention to MSUs at non-peak times literally “pays” in terms of saving real money.

CPU 'tuning' exercises often focus on unnecessary TCB switches. In this case, changes made that reduced TCB switch time saved a ton of CPU - up to 2,000 seconds.

Seeing real end-to-end risks from the VMware guest through the SAN fabric to the Storage LUN is difficult, leading to many SAN Connectivity issues.

This final blog in the mainframe cost reduction series will cover potential CPU reduction opportunities that produce benefits applicable to a specific address space or application.

This blog explores how a non-Db2 expert quickly identified latch contention arising from a Data Sharing Index Split as the root cause of a Db2 delay/slowdown.

Data compression in an IBM SVC Spectrum Virtualize environment may help regain capacity, but hidden performance problems can occur if compressible workloads are not first identified.

Each distributed system platform has unique nuances. It's important for a solution to be capable of getting the detailed performance data capable of supporting vendor-specific architectures.

This blog covers several CPU reduction areas, including, moving work outside the monthly peak R4HA interval, reducing zIIP overflow, reducing XCF volumes, and leveraging Db2 memory to reduce I/Os.

In this blog we examine before-and-after measurements of a recent zHyperWrite implementation for MQ logging in a large z/OS environment.

CPU optimization opportunities applicable across the infrastructure can often by implemented without the involvement of application teams and can benefit a significant portion (or all) of the work across the system.

Learn how a recent unexpected drop in asynchronous response time led to the discovery that one of the network links used for asynchronous replication went down and a permanent performance improvement.

Being able to easily see, filter, compare, and interact with the processor topology enables analysts to easily configure their processor configuration, which is important for reducing CPU cost.